Core signal
Model-to-measurement engineering: MATLAB/Simulink references, C++ implementations, fixed-point notes, Verilog/FPGA architecture, IQ captures, metrics and reports.
10-minute engineering portfolio review
A compact path for reviewers, recruiters and collaborators who want to evaluate practical DSP, FPGA, SDR, C++ and measurement-system evidence without reading every repository first.
Review target
Look for reproducibility: commands, tests, manifests, plots, generated reports, evidence indexes and honest limitations.
Open these first
| Step | Repository | What to check |
|---|---|---|
| 1 | zynq-sdr-course | End-to-end SDR course path from DSP model to HDL, Zynq/AD9363, RF/IQ data and measurement reports. |
| 2 | cpp-dsp-showcase | C++17 DSP kernels with deterministic tests, benchmark tooling and CMake packaging. |
| 3 | optical-demodulator | Coherent optical DSP research flow with CDC comparison, BER/EVM/SNR methodology and IEEE-style assets. |
| 4 | network-quality-assessment | Timestamp credibility, SLA trace schema and synthetic report generation for latency/jitter analysis. |
| 5 | script-toolbox | Repeatable Windows/SSH/Git setup automation with PowerShell quality gates and safety notes. |
What this portfolio is meant to prove
DSPFPGASDRC++VerilogMATLAB/SimulinkMeasurementsTechnical documentationThe strongest evidence is not a single algorithm. It is the repeated engineering pattern across projects: define a signal problem, build a reference model, implement it, verify it, measure it and document the result.