Core signal
Model-to-measurement engineering: MATLAB/Simulink references, C++ implementations, fixed-point notes, Verilog/FPGA architecture, IQ captures, metrics and reports.
10-minute engineering portfolio review
A compact path for reviewers, recruiters and collaborators who want to evaluate practical DSP, FPGA, SDR, C++ and measurement-system evidence without reading every repository first.
Review target
Look for reproducibility: commands, tests, manifests, plots, generated reports, evidence indexes and honest limitations.
Open these first
About ten minutes in total. Each row names what to check, the evidence to open and the current limit.
| Step | Repository | What to check | Evidence to open |
|---|---|---|---|
| 1 3 min | zynq-sdr-course | End-to-end SDR course path from DSP model to HDL, Zynq/AD9363, RF/IQ data and measurement reports. Strongest hardware result: an in-fabric QPSK modem on a two-board 915 MHz link with payload BER ≈4×10−4. Limit: the raw QPSK RF recording stays local; its checksum, manifest, plots and metrics are public. | Reviewer path Flagship reviewer report Current maturity |
| 2 3 min | zynq-lora-phy-positioning | LoRa PHY from MATLAB and recorded SX1262 IQ through fixed-point Simulink and generated HDL to real ZynqSDR reception, PL timestamps and fractional ToA. Latest M9 hardware evidence includes fractional-CFO derotation and split-preamble recovery, 492/492 CRC-valid captures with zero detection misses in the 500-attempt series, and 732/732 CRC-valid packets with zero misses across the combined M9 runs. The published joint timestamp residual stayed within ±0.5 sample. Limit: controlled cable-delay calibration and synchronized multi-receiver TDoA positioning remain open; calibrated 2D TDoA results are still model-level evidence. | MATLAB M1 acceptance Simulink M2 acceptance M9 hardware evidence Roadmap |
| 3 2 min | cpp-dsp-showcase | C++17 DSP kernels (FIR, Goertzel, GCC-PHAT, rational resampling) with deterministic tests, benchmark tooling and CMake packaging. Limit: intentionally compact — sized for study and review, not a complete DSP framework. | Reviewer quick check Algorithm evidence matrix |
| 4 1 min | network-quality-assessment | Timestamp credibility, SLA trace schema and synthetic report generation for latency/jitter analysis. Limit: the CI demo is synthetic; the reviewer checklist separates it from hardware SLA measurements. | Synthetic SLA demo Reviewer checklist Sample result |
| 5 1 min | script-toolbox | Repeatable Windows/SSH/Git setup automation with PowerShell quality gates and safety notes. Limit: Windows-focused; the scripts change system configuration and expect elevated sessions. | CI quality gates Safety model |
What this portfolio is meant to prove
The strongest evidence is not a single algorithm. It is the repeated engineering pattern across projects: define a signal problem, build a reference model, implement it, verify it, measure it and document the result.
After the review
Questions about a specific repository, measurement or implementation detail are welcome.