Alexander Lyubko • lay007
I build and validate communication and signal-processing systems across MATLAB/Simulink, fixed-point DSP, C++/RTL, FPGA and SDR hardware.
The work is evidence-driven: deterministic tests, bit-exact checks, Zynq/AD936x integration, real IQ captures and measured BER, EVM, timing and packet results.
Three flagship public projects show the C++ implementation and hardware-verification sides of the same workflow: reference models, implementation, deterministic verification, hardware integration and measured results.
Reusable DSP kernels with deterministic validation, packaging and optional optimized hot paths rather than isolated algorithm demos.
Evidence: deterministic tests, algorithm evidence matrix, multi-platform CI, optional AVX2 paths and reproducible benchmark tooling.
Open first: Reviewer quick check Case study
DSP/SDR engineering course and reference implementation from models and fixed-point design to RTL, Zynq/AD936x and RF measurements.
Evidence: two-board 915 MHz QPSK link at payload BER ≈4×10−4; fabric loopback BER <5.34×10−7 over 5.6 Mbit.
Open first: Reviewer path Case study
LoRa PHY and precise packet timing from real SX1262 IQ through MATLAB, fixed-point Simulink and generated HDL to ZynqSDR.
Evidence: M9 reached 732/732 CRC-valid captured packets across two hardware runs, with zero detection misses. M11 measured SF7/BW125 FPGA PER for CR 4/5–4/8; at CR 4/5 the 10% PER point was approximately −7.8 dB SNR, versus −8.2 dB for the known-timing model. Multi-receiver calibrated TDoA is not yet demonstrated.
Open first: M9 hardware evidence M11 PER curves Roadmap Case study
Useful supporting projects, intentionally secondary to the DSP/C++/FPGA/SDR portfolio.
Useful when a DSP, FPGA or SDR problem needs an engineer who can move between the mathematical model, implementation details and the measurement bench.
Trace a difficult DSP/communications problem through assumptions, interfaces, timing, numerical behavior and measurable acceptance criteria.
Turn a reference algorithm into fixed-point decisions, shared test vectors and an implementation path for C++ or RTL.
Instrument real hardware, capture evidence and separate RF, clocking, synchronization, numerical and RTL failure modes.
Focused support for DSP, SDR, communications, fixed-point and FPGA work without adding a full-time specialist.
A measurement-driven workflow: metrics close the loop back to MATLAB, C++ DSP, fixed-point decisions and RTL rather than treating hardware validation as the final step.
The strongest part of my profile is the ability to connect mathematical models, hardware constraints and implementation details into one coherent engineering workflow.
Testable FIR, Goertzel, resampling and correlation kernels; CMake packages, deterministic checks and reproducible benchmarks.
Fixed-point analysis, synchronization, transforms, modulation/demodulation and reproducible signal-processing models.
RTL verification, hardware integration, timing, telemetry data paths, RF capture and measurement-driven debugging.
Applied electronics background combined with information security awareness for real devices, infrastructure and specialized development.
Applied engineering work backed by research, teaching, technical writing and invention activity — useful context, but secondary to measured implementation evidence.
Candidate of Technical Sciences, with an analytical research foundation supporting applied work in signal processing, communications and FPGA-oriented development.
Long-term teaching practice helps translate difficult technical material into structured, understandable engineering knowledge and practical workflows.
Experience in technical writing and invention activity complements implementation work with discipline, clarity and a stronger systems perspective.
Typical working stack across modeling, implementation and supporting engineering software.
Open to focused consulting, part-time R&D support and project work in DSP, C++ engineering software, FPGA/SDR systems and communications.
Technical diagnostics, model audits, algorithm-to-implementation work, architecture reviews, engineering tooling and specialized R&D support.