Block 11 bring-up case studies¶
About half of the Block 11 labs are not exercises but the record of getting a modem to work on real hardware. Each records one failure, the experiments that narrowed it down and, eventually, the cause. Read them after the core path, as worked examples of debugging rather than as procedures to repeat.
What the cases teach, in one list¶
- A counter inside the FPGA is not evidence of a radiated signal. Only an independent receiver can say that (case 3).
- A passing test of a neighbouring path proves nothing about the broken one. A healthy DDS tone hid a disconnected data path (case 3).
- Check what was actually built before debugging what it does. A stale block design invalidated weeks of results (case 4).
- Know where your probe is. Five labs measured a healthy signal one block before the block that broke it (case 7).
- Split the failure population before averaging it. A "BER floor" was two different defects (case 8).
- One experiment, one hypothesis. Negative results are results: each eliminated suspect narrowed the search (case 2).
- Simulation and timing closure are necessary, not sufficient. A live A/B test has the veto (cases 5 and 6).
The cases¶
| # | Labs | Symptom | What it turned out to be | Lesson |
|---|---|---|---|---|
| 1 | 11.8–11.11 | The first PL BPSK burst returns no bits; a host IIO capture running at the same time as the burst control fails with a Bus error or a refill timeout. |
An integration problem around the live PL design, not a tuning problem: disabling the axi_gpreg clock-monitor input removed the overlap Bus error. The overlay was cut back to a minimal, boot-safe control path first. |
When the failure depends on what else runs at the same time, stop tuning gains and look at the structure. Keep a known-good baseline and change one thing at a time. |
| 2 | 11.13–11.19 | After the runtime overlay is hot-loaded, tx_valid_count > 0 but rx_valid_count = 0, and the host RX capture times out (errno 110). |
Not the RX common re-init (11.16), not start_offset 0–127 (11.17), not host session state (11.18), not TX settle time (11.19). Lab 11.26 later found that the deployed bitstream had been built from an outdated block design. |
Each lab ruled out one suspect and said so. That record is what made the real cause findable. |
| 3 | 11.20–11.25 | An external RTL-SDR decodes the stock-shell BPSK at BER 0, and sees the DDS tone in both stock and runtime modes, but the runtime PL captures sit at BER ≈ 0.35 with no preamble correlation. | The pages first concluded "TX is fine, RX is broken". The data said otherwise: no PL burst was on the air. After the overlay reload the DAC runs in DDS-only mode and ignores the PL stream (found in 11.26). The DDS tone worked because it never used that stream. | tx_valid_count > 0 proves samples were produced, not transmitted. Labs 11.22–11.25 now carry the correction. |
| 4 | 11.26 | BER stays near 40–50 % on hardware while every simulation passes. | Six defects, found one at a time: the DAC in DDS-only mode; a stale block design whose register map did not match the host (the out-of-context synthesis cache had also hidden RTL fixes); a timing sampler reset only once, so every frame after the first recovered nothing; a wrong sample format; a one-cycle handshake bubble per symbol that under-ran the DAC FIFO and warped time; and a 4-bit preamble lock window that also matched the leading zeros. After the last fix: BER 0 on the chip. | A 50 % BER floor has many possible causes. Fix one, keep a regression test for it, measure again. |
| 5 | 11.33 | A new timing picker passes replay and RTL tests and closes timing. | The live A/B on two boards was worse than the accepted receiver (10–35 % clean attempts against 67.5 %). The candidate was removed. | Simulation passing and timing closure are necessary; the physical A/B decides. |
| 6 | 11.35 | A Gardner timing loop helps lock but not clean frames, and collapses at zero CFO. | The cheap error detector used independent signs on I and Q, so its gain depended on the constellation's rotation. A CFO sweeps the rotation and hid the defect; at zero CFO it showed. A dot-product form fixed the invariance. | Test at the condition that removes the masking variable, and report paired results with confidence intervals. |
| 7 | 11.41 | One payload bit is wrong in every flagged frame, although every measurement of the signal at that symbol is healthy. | The capture tap records the input of the receive chain; the DC blocker is the first block after it, and it was following the data. Five labs measured the right quantity in the wrong place. | Know where the probe is. When a measurement and a symptom disagree, the circuit between them is a suspect. |
| 8 | 11.42 | After the DC-blocker fix, about 8 % of frames are still dirty. | Two populations: single-bit noise errors, and frames with about half the bits wrong from bit 0, i.e. a whole burst decoded in the wrong rotation because the frame sync locked falsely. | Do not average a bimodal failure into one BER; split it and follow the population that carries the signal. |
The remaining Block 11 labs that are not part of the core path (11.9, 11.10, 11.15–11.18, 11.21, 11.23, 11.24) are the individual experiments inside these cases.