Learning routes¶
The course has more than a hundred labs, and not every learner has the same equipment. Pick the route that matches what you have; each one is a subset of the next, so nothing done on an earlier route is wasted. The labs run in the order listed.
| Route | You need | What it covers |
|---|---|---|
| A. Laptop only | Python (python tools/tasks.py install); Icarus Verilog from step A5 |
DSP, sampling, fixed point, modulation and synchronization, RTL simulation, and real recordings that ship with the repository |
| B. + RTL-SDR | an RTL-SDR receiver (about the price of a textbook) and an antenna | your own over-the-air recordings |
| C. + Zynq board | the Zynq-7020 + AD9363 board, cables, attenuators | transmitting, the FPGA receiver on silicon, two-board links |
| D. + bench instruments | NanoVNA, RF attenuators | S-parameters and component measurements |
MATLAB / Simulink are optional throughout: the labs that mention them also run in Python. The one exception is Lab 4.4, which is a Simulink lab; skip it without a licence.
Route A: laptop only¶
A0. Orientation. Read Block 1: Introduction to SDR, Preparing the Software Environment, Hardware Platform of the Course, Bridge from Model to Hardware, Signal Quality Metrics: FFT, SNR, EVM and BER, FFT and Spectral Analysis, Link Budget in SDR Systems, Fixed-Point Effects in DSP and FPGA.
A1. Signals, sampling and spectra
- Lab 2.1: Sampling Axis and Interpretation
- Lab 2.2: Aliasing Sweep
- Lab 2.3: I/Q Interpretation and Mirrored Spectrum
- Lab 3.1: FFT Windows and Spectral Leakage
- Lab 3.2: FIR Low-Pass Filtering of IQ Data
- Lab 3.3: Digital Mixing and Frequency Shift
- Lab 3.4: Decimation with Anti-Aliasing Filter
- Lab 3.5: FFT complexity and selected-bin trade-off
- Lab 3.6: Convolution and correlation for SDR
- Lab 3.7: Window trade-offs and weak-signal detection
A2. Real recordings without hardware. The repository ships real RTL-SDR and board recordings; these labs read them.
- Lab 9.1: IQ File Format and Metadata
- Lab 9.2: Read CI16 IQ and Analyze Spectrum
- Lab 9.3: Multi-Format IQ Reader
- Lab 9.4: Read WAV IQ and Analyze Spectrum
- Lab 9.5: Synthetic QPSK replay and constellation analysis
- Lab 6.4: Synthetic RF Capture Analysis
- Lab 6.7. Zero-IF artifacts: DC component, mirror and tune offset
A3. Fixed point
- Lab 4.1: Fixed-Point FIR Filtering
- Lab 4.2: Fixed-Point Digital Mixer
- Lab 4.3: BPSK fixed-point chain
- Lab 4.4: BPSK Simulink chain and ideal BER vs SNR
A4. TX/RX chains, modulation and synchronization
- Lab 7.1: TX/RX Chain Architecture
- Lab 7.2: DUC/DDC Frequency Translation
- Lab 7.3: TX/RX Loopback Metrics
- Lab 7.4: Packet receiver chain and frame detection
- Lab 7.5: CIC decimator for SDR receiver chains
- Lab 8.1: Carrier Frequency Offset Estimation and Correction
- Lab 8.2: Phase Offset Estimation and Decision-Directed Correction
- Lab 8.3: Symbol Timing Offset and Recovery
- Lab 8.4: End-to-End Synchronization Chain
- Lab 8.5: OFDM mini link (CP, pilots, sync, equalization)
- Lab 8.6: Channel coding BER comparison with interleaving
- Lab 8.7. SNR is not enough: BER/EVM traps
- Lab 8.8: QPSK modem, impairments and BER
- Lab 8.9: QPSK carrier recovery (decision-directed Costas loop)
- Lab 8.10: OFDM PAPR, clipping and spectral regrowth
- Lab 8.11. 16-QAM bridge: BER, EVM and implementation limits
- Lab 8.12. GFSK: BT, occupied bandwidth and discriminator BER
- Lab 8.13: DSSS acquisition and processing gain
- Lab 8.20: CSS chirp waveform and symbol mapping
- Lab 8.21: CSS dechirp and FFT detector
- Lab 8.22: Packet-level CSS synchronization and PER
- Lab 6.2: Gain Staging and Overload
- Lab 6.5: RF impairment calibration (DC, IQ imbalance, LO leakage)
A5. RTL simulation (install Icarus Verilog; Vivado is not needed)
- Lab 5.1: Streaming DSP Interface and Testbench
- Lab 5.2: FIR RTL Mapping
- Lab 5.3: Fixed-Point NCO Mixer RTL
- Lab 5.4: AXI-Stream Wrapper
- Lab 5.5: Float vs fixed-point vs RTL comparison
- Lab 5.6: BPSK RRC TX FIR RTL
- Lab 5.7: BPSK 8x symbol upsampler
- Lab 5.8: BPSK RX matched filter and bit recovery
- Lab 5.9: BPSK framed TX/RX loopback top-level
- Lab 5.10: Zynq-ready BPSK BER top-level
- Lab 8.14. OFDM RTL: mapper to equalized loopback
A6. System design and reports
- Lab 10.1: Passive RC Filter
- Lab 10.2: Simple Attenuator Pad
- Lab 10.3: RF Measurement Safety Checklist
- Lab 10.4: KiCad Schematic Mini-Project
- Lab 11.1: Project Requirements and System Architecture
- Lab 11.2: End-to-End Simulation Package
- Lab 11.3: FPGA/RF Integration Checklist
- Lab 11.4: Final Measurement Report
- Lab 11.5: AXI DMA pipeline latency and jitter
- Lab 11.6: Measurement uncertainty budget and reporting
- Project 12.1: QPSK Modem Final Project
- Project 12.3: FPGA DSP Block Final Project
Route B: add an RTL-SDR¶
Everything on route A, plus:
- Lab 1.0: First RF Observation with RTL-SDR
- Lab 6.1: RF Frequency Plan
- Project 12.2: RF Capture Analysis Final Project
Record your own WAV in Lab 1.0 and analyse it with the scripts of Labs 9.4 and 6.4 instead of the shipped recordings.
Route C: add the Zynq board¶
Everything on routes A and B, plus the board itself:
- Lab 1.1: Controlled Zynq DDS Tone with RTL-SDR
- Lab 6.3: AD9363 Settings and iio_attr Quick Reference
- Lab 6.6: Zynq RX-only observation on the clean image
- Lab 6.8: Zynq stock-shell OTA DDS tone observation
- Lab 6.9: RTL-SDR vs AD936x receiver quality and ADC resolution
- Lab 6.10: AGC/LNA Gain-Transition Phase-Discontinuity Analysis
- Lab 6.11: dBm vs dBFS power calibration
- Lab 5.11: AXI-Lite control wrapper for the BPSK BER top-level
- Lab 5.12. PS↔PL message mailbox: the first meaningful Zynq bridge
- Lab 8.15. Real-hardware BPSK: spectrum, constellation and SNR/EVM
Then the integrated project of Block 11, the core path from a PS-controlled modem to a two-board link:
- Lab 11.7: PS-side AXI-Lite BPSK bring-up
- Lab 11.14: Stock-shell host BPSK OTA fallback
- Lab 11.27: Runtime QPSK digital-loopback BER
- Lab 11.28: Runtime QPSK through an external RTL-SDR
- Lab 11.29: Cold-boot BER reliability campaign
- Lab 11.30: Coarse-CFO estimator on a real two-board link
- Lab 11.31: Coarse-CFO estimator stress sweep
- Lab 11.32: Two-board coarse-CFO acquisition in the FPGA fabric
- Lab 11.34: Continuous QPSK Gardner timing recovery
- Lab 11.38: ZynqSDR TX → IQ capture → offline receiver
- Lab 11.45. Differential QPSK + a longer preamble: the rotation floor, gone
- Lab 11.46: A message from one Zynq console to another
- Project 12.4: Full SDR Measurement Report
The other Block 11 labs (11.8–11.26, 11.33, 11.35, 11.41, 11.42) are the bring-up history of that path: each records one failure, how it was found and how it was fixed. Read them as case studies once the core path is clear: Block 11 bring-up case studies summarises each one as symptom, cause and lesson.
Route D: add bench instruments¶
- Lab 10.5. NanoVNA and RF Demo Kit: S11/S21, VSWR and Smith Chart
- Lab 10.6. Digital RF Attenuator: Step, Range and Linearity Check
What each block assumes¶
| Block | Comes after | New tools |
|---|---|---|
| 1. Introduction | - | Python, a spectrum viewer |
| 2. Signals and sampling | Block 1 | - |
| 3. DSP basics | Block 2 | - |
| 4. Fixed point | Block 3 | (MATLAB / Simulink optional) |
| 5. FPGA / HDL | Blocks 3–4 | Icarus Verilog; Vivado only for synthesis |
| 6. RF frontend | Blocks 2–3 | RTL-SDR or the board for the live parts |
| 7. TX/RX chains | Blocks 3, 6 | - |
| 8. Modulation and synchronization | Block 7 | Icarus Verilog for 8.14 |
| 9. Recording and analysis | Block 2 | - |
| 10. Electronics and KiCad | Block 1 | KiCad; NanoVNA for 10.5–10.6 |
| 11. Integrated project | Blocks 5–8 | the board |
| 12. Final projects | the route you followed | - |
Report format¶
Every lab report contains the goal, the equipment, the parameters, the procedure, the plots or screenshots and an engineering conclusion with numbers. See the lab report template.