Course Overview¶
A bilingual SDR course from theory to board-level implementation.
This is the English learning path: the same course pipeline as the main page, navigated block by block.
MATLAB / Simulink
Fixed-point DSP
FPGA / HDL
Zynq-7020
AD9363
RTL-SDR
Quick navigation¶
Learning routes
Which labs to do, in which order, with a laptop only, an RTL-SDR or the Zynq board.
Open →Hardware debug as part of the model
Why debug instrumentation belongs in the design, not bolted on afterward.
Open →Course blocks¶
| Block | Topic |
|---|---|
| 1 | Introduction to SDR: tools, signals and first reception concepts |
| 2 | Signals and Sampling: spectrum, aliasing, complex baseband and IQ |
| 3 | DSP Basics: FFT, FIR, windows, mixing and decimation |
| 4 | Simulink and Fixed-Point: numeric formats, scaling and quantization |
| 5 | FPGA / HDL Flow, streaming interfaces, Verilog and testbenches |
| 6 | RF Frontend and AD9363: frequency plans, gain staging and AD9363 settings |
| 7 | TX/RX Chains: DUC, DDC, loopback and packet-level metrics |
| 8 | Modulation and Synchronization: CFO, phase, timing, EVM and BER |
| 9 | Recording and Analysis Tools: metadata, formats, replay and quality checks |
| 10 | KiCad and Basic Electronics: attenuators, filters and RF safety |
| 11 | Integrated SDR Project: model, implementation, capture and report |
| 12 | Final Projects: a project of your own, from proposal to measured report |