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Zynq SDR Course
Lab 11.24
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DSP foundation track
DSP → FPGA Bridge
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Zynq SDR Course
Lay007/zynq-sdr-course
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System
System
Model → FPGA → RF → Measurement
Reproducible engineering route
Hardware experiment roadmap
SDR platform teardown template
Hardware checklist
Hardware bring-up checklist
RF safety guide
End-to-end SDR demo roadmap
End-to-end tone demo report
End-to-end BPSK reference report
End-to-end QPSK hardware demo
Dual-modem final implementation report
SDR measurement report template
Digital-link metric calculations
HDL smoke verification
Experiment manifests
Lab 1: Tone → RF → IQ → Analysis
Lab 2: AM/FM Spectrum
Lab 3: QPSK Constellation
Course demo dashboard
Demo lab flow
Visual course map
Portfolio view
DSP foundation track
DSP → FPGA Bridge
C++ ↔ MATLAB bridge
CIC fixed-point FPGA bridge
FPGA streaming principles
Measurement Errors
Course Quality
Course Quality
Course status
Student path
Reviewer path
Reviewer one-page summary
Reviewer acceptance checklist
Instructor guide
Quality roadmap
Course readiness matrix
Completion matrix
Lab index
CI matrix
Reproducibility guide
Lab contribution guide
Lab report template
IQ metadata guide
IQ dataset manifest guide
Measurement uncertainty guide
Real data policy
SDR / DSP / RF glossary
Block maturity matrix
Course quality gates
Lab review checklist
Reproducibility checklist
Student CI grading guide
Hardware validation backlog
Hardware evidence index
Block 11 hardware bring-up summary
Block 5 FPGA evidence
IQ demo dataset manifest
FPGA resource report template
Final project grading rubric
Final project example report
Release checklist
Release notes v0.1.0
ADR 0001: AI-assisted engineering workflow
Demo (IEEE figures)
GitHub demo notes
IEEE-style guide
Русский
Русский
Обзор курса
Структура курса
Лабораторный трек
Медиа-гайд
Статус курса
Проектирование debug-сигналов
Аппаратная отладка по проекту
Блоки курса
Блоки курса
01. Введение в SDR
02. Сигналы и дискретизация
03. Базовые DSP-операции
03A. DSP engineering notes
04. Simulink и fixed-point
04A. Fixed-point workflow
05. FPGA / HDL flow
05A. HDL/FPGA workflow
06. RF frontend и AD9363
06A. RF frontend workflow
06B. AD936x zero-IF architecture
07. TX/RX chains
07A. TX/RX chain workflow
08. Modulation and synchronization
08A. Modulation sync workflow
09. Recording and analysis tools
09A. IQ recording and analysis workflow
10. KiCad and basic electronics
10A. Electronics and KiCad workflow
11. Integrated SDR project
11A. Integrated SDR project workflow
12. Final projects
12A. Final project track
Лаборатории Block 1
Лаборатории Block 1
Lab 1.0 — Первое наблюдение эфира через RTL-SDR
Lab 1.1 — Управляемый DDS-тон Zynq с приемом на RTL-SDR
Лаборатории Block 2
Лаборатории Block 2
Lab 2.1 — Частотная ось дискретизации и интерпретация
Lab 2.2 — Aliasing sweep
Lab 2.3 — Интерпретация I/Q и mirrored spectrum
Лаборатории Block 3
Лаборатории Block 3
Lab 3.1 — FFT windows
Lab 3.2 — FIR low-pass
Lab 3.3 — Digital mixing
Lab 3.4 — Decimation
Lab 3.5 — FFT complexity
Lab 3.6 — Convolution and correlation
Lab 3.7 — Window trade-offs
Лаборатории Block 4
Лаборатории Block 4
Lab 4.1 — Fixed-point FIR
Lab 4.2 — Fixed-point digital mixer
Lab 4.3 — BPSK fixed-point chain
Lab 4.4 — BPSK Simulink chain and ideal BER vs SNR
Лаборатории Block 5
Лаборатории Block 5
Lab 5.1 — Streaming interface and testbench
Lab 5.2 — FIR RTL mapping
Lab 5.3 — NCO mixer RTL
Lab 5.4 — AXI-Stream wrapper
Lab 5.5 — Float vs fixed vs RTL comparison
Lab 5.6 — BPSK RRC TX FIR RTL
Lab 5.7 — BPSK 8x symbol upsampler
Lab 5.8 — BPSK RX matched filter and bit recovery
Lab 5.9 — BPSK framed TX/RX loopback top-level
Lab 5.10 — Zynq-ready BPSK BER top-level
Lab 5.11 — AXI-Lite control wrapper for the BPSK BER top-level
Лаборатории Block 6
Лаборатории Block 6
Lab 6.1 — RF frequency plan
Lab 6.2 — Gain staging and overload
Lab 6.3 — AD9363 settings and iio_attr
Lab 6.4 — Synthetic RF capture analysis
Lab 6.5 — RF impairment calibration
Lab 6.6 — Zynq RX-only observation on the clean image
Lab 6.7 — Zero-IF artifacts
Lab 6.8 — Zynq stock-shell OTA DDS tone observation
Лаборатории Block 7
Лаборатории Block 7
Lab 7.1 — TX/RX chain architecture
Lab 7.2 — DUC/DDC frequency translation
Lab 7.3 — TX/RX loopback metrics
Lab 7.4 — Packet receiver detection
Lab 7.5 — CIC decimator
Лаборатории Block 8
Лаборатории Block 8
Lab 8.1 — CFO estimation and correction
Lab 8.2 — Phase offset correction
Lab 8.3 — Timing recovery
Lab 8.4 — End-to-end sync chain
Lab 8.5 — OFDM mini link
Lab 8.6 — Channel coding BER comparison
Lab 8.7 — SNR vs BER traps
Лаборатории Block 9
Лаборатории Block 9
Lab 9.1 — IQ file format and metadata
Lab 9.2 — Read CI16 IQ and analyze spectrum
Lab 9.3 — Multi-format IQ reader
Lab 9.4 — Чтение WAV IQ и офлайн-анализ
Lab 9.5 — Synthetic QPSK replay and constellation analysis
Лаборатории Block 10
Лаборатории Block 10
Lab 10.1 — Passive RC filter
Lab 10.2 — Simple attenuator pad
Lab 10.3 — RF measurement safety checklist
Lab 10.4 — KiCad schematic mini-project
Лаборатории Block 11
Лаборатории Block 11
Lab 11.1 — Project requirements and architecture
Lab 11.2 — End-to-end simulation package
Lab 11.3 — FPGA/RF integration checklist
Lab 11.4 — Final measurement report
Lab 11.5 — AXI DMA latency and jitter
Lab 11.6 — Measurement uncertainty budget
Lab 11.7 — PS-side AXI-Lite BPSK bring-up
Lab 11.8 — AD9361 gpreg BPSK overlay
Lab 11.9 — AD9361 RF discovery sweep
Lab 11.10 — Timed IIO burst capture
Lab 11.11 — IIO vs gpreg contention probe
Lab 11.13 — Stock vs runtime RX compare
Lab 11.14 — Stock-shell host BPSK OTA measurement
Lab 11.15 — Runtime bridge RX with host TX probe
Lab 11.16 — Runtime RX common re-init probe
Lab 11.17 — Runtime RX re-init start-offset sweep
Lab 11.18 — Runtime RX re-init fresh-session sweep
Lab 11.19 — Runtime bridge_txrx_mux self-timed bring-up
Lab 11.20 — Read RTL-SDR WAV OTA BPSK BER
Lab 11.21 — Capture RTL-SDR monitor WAV (stock-shell BPSK)
Lab 11.22 — Capture RTL-SDR monitor WAV (runtime PL BPSK)
Lab 11.23 — Runtime PL RTL-SDR attenuation sweep
Lab 11.24 — Capture DDS tone RTL-SDR monitor WAV
Lab 11.25 — Stock vs runtime DDS tone sweep
Lab 11.26 — Runtime PL BPSK OTA: DDS-bypass fix
Lab 11.27 — Runtime QPSK digital-loopback BER
Lab 11.28 — Runtime QPSK через RTL-SDR
Проекты Block 12
Проекты Block 12
Project 12.1 — QPSK modem final project
Project 12.2 — RF capture analysis final project
Project 12.3 — FPGA DSP block final project
Project 12.4 — Full SDR measurement report
English
English
Course overview
Course structure
Lab track
Media guide
Debug waveform design
Hardware debug by design
Course blocks
Course blocks
01. Intro to SDR
02. Signals and sampling
03. DSP basics
03A. DSP engineering notes
04. Simulink and fixed-point
04A. Fixed-point workflow
05. FPGA / HDL flow
05A. HDL/FPGA workflow
06. RF frontend and AD9363
06A. RF frontend workflow
06B. AD936x zero-IF architecture
07. TX/RX chains
07A. TX/RX chain workflow
08. Modulation and synchronization
08A. Modulation sync workflow
09. Recording and analysis tools
09A. IQ recording and analysis workflow
10. KiCad and basic electronics
10A. Electronics and KiCad workflow
11. Integrated SDR project
11A. Integrated SDR project workflow
12. Final projects
12A. Final project track
Block 1 labs
Block 1 labs
Lab 1.0 — First RF Observation with RTL-SDR
Lab 1.1 — Controlled Zynq DDS Tone with RTL-SDR
Block 2 labs
Block 2 labs
Lab 2.1 — Sampling axis and interpretation
Lab 2.2 — Aliasing sweep
Lab 2.3 — I/Q interpretation and mirrored spectrum
Block 3 labs
Block 3 labs
Lab 3.1 — FFT windows
Lab 3.2 — FIR low-pass
Lab 3.3 — Digital mixing
Lab 3.4 — Decimation
Lab 3.5 — FFT complexity
Lab 3.6 — Convolution and correlation
Lab 3.7 — Window trade-offs
Block 4 labs
Block 4 labs
Lab 4.1 — Fixed-point FIR
Lab 4.2 — Fixed-point digital mixer
Lab 4.3 — BPSK fixed-point chain
Lab 4.4 — BPSK Simulink chain and ideal BER vs SNR
Block 5 labs
Block 5 labs
Lab 5.1 — Streaming interface and testbench
Lab 5.2 — FIR RTL mapping
Lab 5.3 — NCO mixer RTL
Lab 5.4 — AXI-Stream wrapper
Lab 5.5 — Float vs fixed vs RTL comparison
Lab 5.6 — BPSK RRC TX FIR RTL
Lab 5.7 — BPSK 8x symbol upsampler
Lab 5.8 — BPSK RX matched filter and bit recovery
Lab 5.9 — BPSK framed TX/RX loopback top-level
Lab 5.10 — Zynq-ready BPSK BER top-level
Lab 5.11 — AXI-Lite control wrapper for the BPSK BER top-level
Block 6 labs
Block 6 labs
Lab 6.1 — RF frequency plan
Lab 6.2 — Gain staging and overload
Lab 6.3 — AD9363 settings and iio_attr
Lab 6.4 — Synthetic RF capture analysis
Lab 6.5 — RF impairment calibration
Lab 6.6 — Zynq RX-only observation on the clean image
Lab 6.7 — Zero-IF artifacts
Lab 6.8 — Zynq stock-shell OTA DDS tone observation
Block 7 labs
Block 7 labs
Lab 7.1 — TX/RX chain architecture
Lab 7.2 — DUC/DDC frequency translation
Lab 7.3 — TX/RX loopback metrics
Lab 7.4 — Packet receiver detection
Lab 7.5 — CIC decimator
Block 8 labs
Block 8 labs
Lab 8.1 — CFO estimation and correction
Lab 8.2 — Phase offset correction
Lab 8.3 — Timing recovery
Lab 8.4 — End-to-end sync chain
Lab 8.5 — OFDM mini link
Lab 8.6 — Channel coding BER comparison
Block 9 labs
Block 9 labs
Lab 9.1 — IQ file format and metadata
Lab 9.2 — Read CI16 IQ and analyze spectrum
Lab 9.3 — Multi-format IQ reader
Lab 9.4 — Read WAV IQ and analyze spectrum
Lab 9.5 — Synthetic QPSK replay and constellation analysis
Block 10 labs
Block 10 labs
Lab 10.1 — Passive RC filter
Lab 10.2 — Simple attenuator pad
Lab 10.3 — RF measurement safety checklist
Lab 10.4 — KiCad schematic mini-project
Block 11 labs
Block 11 labs
Lab 11.1 — Project requirements and architecture
Lab 11.2 — End-to-end simulation package
Lab 11.3 — FPGA/RF integration checklist
Lab 11.4 — Final measurement report
Lab 11.5 — AXI DMA latency and jitter
Lab 11.6 — Measurement uncertainty budget
Lab 11.7 — PS-side AXI-Lite BPSK bring-up
Lab 11.8 — AD9361 gpreg BPSK overlay
Lab 11.9 — AD9361 RF discovery sweep
Lab 11.10 — Timed IIO burst capture
Lab 11.11 — IIO vs gpreg contention probe
Lab 11.13 — Stock vs runtime RX compare
Lab 11.14 — Stock-shell host BPSK OTA measurement
Lab 11.15 — Runtime bridge RX with host TX probe
Lab 11.16 — Runtime RX common re-init probe
Lab 11.17 — Runtime RX re-init start-offset sweep
Lab 11.18 — Runtime RX re-init fresh-session sweep
Lab 11.19 — Runtime bridge_txrx_mux self-timed bring-up
Lab 11.20 — Read RTL-SDR WAV OTA BPSK BER
Lab 11.21 — Capture RTL-SDR monitor WAV (stock-shell BPSK)
Lab 11.22 — Capture RTL-SDR monitor WAV (runtime PL BPSK)
Lab 11.23 — Runtime PL RTL-SDR attenuation sweep
Lab 11.24 — Capture DDS tone RTL-SDR monitor WAV
Lab 11.25 — Stock vs runtime DDS tone sweep
Lab 11.26 — Runtime PL BPSK OTA: DDS-bypass fix
Lab 11.27 — Runtime QPSK digital-loopback BER
Lab 11.28 — Runtime QPSK through RTL-SDR
Block 12 projects
Block 12 projects
Project 12.1 — QPSK modem final project
Project 12.2 — RF capture analysis final project
Project 12.3 — FPGA DSP block final project
Project 12.4 — Full SDR measurement report
Lab 11.24
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